DocumentCode :
2142091
Title :
Strained silicon dynamic threshold voltage MOSFETs for low voltage and ultra high speed CMOS circuits
Author :
Gu, Weiying ; Liang, Renrong ; Zhao, Mei ; Xu, Jun
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
134
Lastpage :
137
Abstract :
With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold voltage technique with strained silicon technique is explored and demonstrated on bulk silicon substrate. The strained silicon DT NMOS exhibit a lower subthreshold swing of 66 mV/dec and a remarkably higher saturate drain current of 10.9X at VGS=0.5 V, compared to standard strained silicon NMOS. As the result of these improvements, the strained silicon DT-CMOS inverter remains eligible with the power supply voltage down to 0.3 V.
Keywords :
CMOS digital integrated circuits; silicon; very high speed integrated circuits; NMOS; Si; bulk silicon substrate; drain current; strained silicon DT-CMOS inverter; strained silicon dynamic threshold voltage MOSFETs; ultrahigh speed CMOS circuits; Bipolar transistors; Buffer layers; CMOS digital integrated circuits; Germanium silicon alloys; Low voltage; MOS devices; MOSFETs; Power supplies; Silicon germanium; Threshold voltage; CMOS; dynamic threshold voltage; low voltage; strained silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4734491
Filename :
4734491
Link To Document :
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