Assessing chip-level impact of double patterning lithography

Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32 nm and 22 nm process nodes, relative to costlier technology options such as high refractive index materials, extreme ultraviolet (EUV), or e-beam lithography. DPL implements patterns on a single layer using either additional masks (e.g., double exposure or double patterning) or many additional processing steps (e.g., spacer double patterning). Overlay between the two layers introduces additional variability in both front-end-of-line (FEOL) and back-end-of-line (BEOL) by means of coupling capacitance variation. FEOL variability can be incorporated into standard characterization. However, the impacts of overlay in BEOL require new circuit analysis techniques. Furthermore, such techniques can guide technology developers toward DPL technology options that will have least variability impact on circuit performance. Today, the industry is nearing a critical juncture for choosing among various DPL technology options and process control capabilities. Accordingly, a rigorous, efficient framework is needed for variational performance analyses at chip level, and across many DPL technology options. Once a DPL method is chosen, a chip-level framework similar to what we present here will be required for circuit analysis and optimization. In this paper, we first analyze mechanisms of space and linewidth variation arising from overlay in various double patterning lithography options. We then develop a foundation of both TCAD-based and chip-level methods, along with an effective design of experiments, to assess electrical impacts of BEOL variations. We conclude with an assessment of relative viabilities of DPL technology options under a range of process control scenarios.