DocumentCode :
2142577
Title :
New 3D chip stacking SIP technology by wire-on-bump (WOB) and bump-on-flex (BOF)
Author :
Lee, Baik-Woo ; Tsai, Jui-Yun ; Jin, Hotae ; Yoon, Chong K. ; Tummala, Rao R.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
fYear :
0
fDate :
0-0 0
Abstract :
Two new 3D chip stacking technologies, WOB (wire-on-bumps) and BOF (bump-on-flex), are proposed and demonstrated with their prototypes. The WOB and BOF technologies are to stack especially memory chips and connect peripheral bumps on the chips vertically by metal wires and by flex-circuit, respectively. These new 3D chip stacking concepts have several advantages over conventional technologies, such as a lower cost than Si through-via process, unlimited number of stacked chips at a smaller package volume and a faster signal speed than wire bonding method. In this paper, the first demonstrations of the prototypes are described by emphasizing their assembly process and thermo-mechanical modeling. Thermal cycle (TC) test was also performed and some of the TC test results were reported
Keywords :
flexible electronics; integrated memory circuits; lead bonding; system-in-package; 3D chip stacking; bump-on-flex; memory chips; system-in-package technology; thermal cycle test; thermomechanical modeling; wire bonding; wire-on-bump; Assembly; Bonding; Costs; Packaging; Prototypes; Signal processing; Stacking; Testing; Thermomechanical processes; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
1-4244-0152-6
Type :
conf
DOI :
10.1109/ECTC.2006.1645752
Filename :
1645752
Link To Document :
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