Source/Drain junction integration issues in submicron Ge MOSFETs

Source/Drain (S/D) engineering in Ge MOSFETs is a complex interplay of various factors, including ion implantation and annealing conditions, electrical activation, the defectiveness of the starting substrate and the contact technology. Some of these aspects will be covered in the following manuscript. It is shown that the formation of highly n-type doped S/D regions suffers from a concentration-enhanced diffusion and an activation ceiling at 5-6 × 10¹⁹ cm^-3, which is insufficient for the (sub)-22 nm CMOS node. Techniques to reduce the enhanced diffusion, like co-implantation with N or C or ultra-fast annealing are discussed, but at the same time do not seem to break the activation barrier. The formation of highly B-doped p⁺ junctions, on the other hand, does not suffer from enhanced diffusion, while active concentrations in the low 10²⁰ cm^-3 range can be achieved with standard Rapid Thermal Annealing. Only for low-energy B implants typical for extensions, evidence of interstitial-mediated Transient-Enhanced Diffusion (TED) is obtained. The main issue for p⁺ S/D-junctions appears to be the fine-tuning of the halo implantation. It is shown that the junction leakage current increases quasi-exponentially with higher halo doping concentration. It is, finally, shown that the implementation of a NiGe contact metallization can give rise to a higher perimeter leakage current, associated with the formation of voids.