Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation

This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single V_DD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (V_MIN). Single-ended write is accomplished in two phases using dual word-lines. Finally, we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing, for the same bitcell area.