Analysis of breakdown characteristics of 40nm PD SOI NMOS device considering STI-induced mechanical stress effect

Author

Kuo, J.B. ; Su, V.C. ; Lin, I.S. ; Chen, D. ; Lin, G.S. ; Yeh, C.S. ; Tsai, C.T. ; Ma, M.

Author_Institution

Dept of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

235

Lastpage

238

Abstract

This paper reports an analysis of the STI-induced mechanical stress-related breakdown characteristics of the 40 nm PD SOI NMOS device with a closed-form formula. As verified by the experimentally measured data, the 2D simulation results and the closed-form formula, the breakdown voltage becomes higher for the device with a smaller S/D length of 0.17 Â¿m due to the weaker function of the parasitic bipolar device, offset by the stronger impact ionization in the post-pinchoff region. The breakdown voltage of this PD SOI NMOS device is affected strongly by the STI-induced mechanical stress effect when the S/D length is smaller than 0.2 Â¿m.

Keywords

CMOS integrated circuits; MOSFET; electric breakdown; silicon-on-insulator; PD SOI NMOS device; STI-induced mechanical stress effect; breakdown characteristic analysis; breakdown voltage; closed-form formula; post-pinchoff region; silicon-on-insulator; size 0.17 mum; size 40 nm; Current measurement; Electric breakdown; Impact ionization; Length measurement; MOS devices; Nanoscale devices; Photonic band gap; Stress; Thin film devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734515

Filename

4734515