• DocumentCode
    2143000
  • Title

    Off-state leakage current modeling in low-power/high-performance partially-depleted (PD) floating-body (FB) SOI MOSFETs

  • Author

    Chen, Qiang ; Goo, Jung-Suk ; Ly, Tran ; Chandrasekaran, Karthik ; Wu, Zhi-Yuan ; Thuruthiyil, Ciby ; Icel, Ali B.

  • Author_Institution
    Adv. Micro Devices, Inc., Sunnyvale, CA, USA
  • fYear
    2008
  • fDate
    20-23 Oct. 2008
  • Firstpage
    301
  • Lastpage
    304
  • Abstract
    Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying physical mechanism, i.e., the FB effect, is also shown to be responsible for observed varying drain-induced-barrier-lowering (DIBL) or highly non-linear dependence of the threshold voltage on drain voltage. While characterization of parasitic currents may present a challenge because of unconventional geometry dependences, the off-state leakage current and its fitting accuracy may be used as an indirect, effective figure of merit.
  • Keywords
    CMOS integrated circuits; MOSFET; elemental semiconductors; leakage currents; low-power electronics; semiconductor device models; silicon; silicon-on-insulator; Si; drain voltage; drain-induced-barrier-lowering variation; lower-power/high-performance technology; off-state leakage current modeling; parasitic current modeling; partially-depleted floating-body SOI MOSFETs; silicon-on-insulator; size 65 nm; threshold voltage; CMOS technology; Energy consumption; Geometry; Impact ionization; Integrated circuit technology; Leakage current; MOSFETs; Silicon on insulator technology; Threshold voltage; Tunneling; Drain-induced barrier lowering (DIBL); Floating-body (FB) effect; Leakage current; Partially-depleted (PD); Silicon-on-insulator (SOI); Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-2185-5
  • Electronic_ISBN
    978-1-4244-2186-2
  • Type

    conf

  • DOI
    10.1109/ICSICT.2008.4734523
  • Filename
    4734523