DocumentCode :
2143389
Title :
Electrostatic discharge protection framework for mixed-signal high voltage CMOS applications
Author :
Salcedo, Javier A. ; Zhu, Haiyang ; Righter, Alan W. ; Hajjar, Jean-Jacques
Author_Institution :
Analog Devices, Wilmington, MA, USA
fYear :
2008
fDate :
20-23 Oct. 2008
Firstpage :
329
Lastpage :
332
Abstract :
Electrostatic discharge (ESD) protection requirements for high voltage (HV) MOS technology are continuously evolving and increasingly stringent. To address the ever changing technology ESD constraints, a method for design, characterization, and integration of reliable mixed-signal HV MOS ESD solutions is introduced in this study. The dynamic response, design trade-offs and ESD verification in two HV CMOS-based technologies are discussed and depicted via fast transient and quasi-static measurements in the ESD-time domain.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; power integrated circuits; ESD-time domain; electrostatic discharge protection framework; mixed-signal high voltage CMOS applications; quasistatic transmission line pulsed measurements; very fast transmission line pulsed measurements; CMOS process; CMOS technology; Circuit topology; Clamps; Dielectrics; Electrostatic discharge; Isolation technology; Protection; Pulse measurements; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
Type :
conf
DOI :
10.1109/ICSICT.2008.4734538
Filename :
4734538
Link To Document :
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