A novel ESD protection circuit applied in high-speed CMOS IC

Author

Zhang, Bing ; Chai, Changchun ; Yang, Yintang

Author_Institution

Key Lab. of Minist. of Educ. for Wide Band-gap Semicond. Mater. Devices, Xidian Univ., Xian, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

345

Lastpage

348

Abstract

A new electrostatic discharge (ESD) protection circuit based on a standard of 0.6 Â¿m CMOS p-well technology has been designed and fabricated according to the request of trigger voltage, chip area and static current to high-speed CMOS IC. The new protection circuit was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new ESD protection circuit has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.

Keywords

CMOS integrated circuits; electrostatic discharge; high-speed integrated circuits; integrated circuit design; ESD protection circuit; chip area; electrostatic discharge; high-speed CMOS IC; human-body mode test; multi-project wafer fabrication; transmission line pulse generator system; trigger voltage; CMOS integrated circuits; CMOS technology; Circuit testing; Electrostatic discharge; Fabrication; High speed integrated circuits; Integrated circuit testing; Protection; System testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734542

Filename

4734542