Deep-submicron tungsten gate CMOS technology

A tungsten-gate CMOS technology has been developed using a low-impurity selective epi-channel and thin gate oxide. The use of this technology leads to a reduction in threshold-voltage sensitivity to process fluctuations such as epi-channel concentration and gate-oxide thickness. The short-channel effect for deep submicron gate MOSFETs can be suppressed by a 50 approximately 10-nm-thick epi-layer with an abrupt impurity profile. Device characteristics for the tungsten gate show several advantages over those for the present poly-Si gate, including approximately 30% larger transconductance and small threshold slope values (80 approximately 85 mV/decade) that results in a large on/off ratio.<>