Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS

Reliability is one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to transistor degradation mechanisms like NBTI/PBTI or soft gate breakdown cause time-dependent circuit performance degradation. Variability and mismatch between transistors only makes this more severe, while at the same time transistor aging can increase the variability and mismatch in the circuit over time. Finally, in advanced nanometer CMOS, the aging phenomena themselves become discrete, with both the time and the impact of degradation being fully stochastic. This paper explores these problems by means of a circuit example, indicating the time-dependent stochastic nature of offset in a comparator and its impact in flash A/D converters.