DocumentCode
2143596
Title
A novel two-dimensional scan-control scheme for test-cost reduction
Author
Lin, Chia-Yi ; Chen, Hung-Ming
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2010
fDate
22-24 March 2010
Firstpage
237
Lastpage
243
Abstract
This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don´t care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC´99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.
Keywords
cost reduction; integrated circuit testing; multiple scan chain design; test time reduction; test-cost reduction; two-dimensional scan shift control concept; Automatic testing; Benchmark testing; Circuit testing; Costs; Design engineering; Electronic equipment testing; Encoding; Pins; Power engineering and energy; Test pattern generators; Scan chain; Test-cost; low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location
San Jose, CA
ISSN
1948-3287
Print_ISBN
978-1-4244-6454-8
Type
conf
DOI
10.1109/ISQED.2010.5450439
Filename
5450439
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