Title :
Scalability of PCMO-based resistive switch device in DSM technologies
Author :
Chen, Yiran ; Tian, Wei ; Li, Hai Helen ; Wang, Xiaobin ; Zhu, Wenzhong
Author_Institution :
Seagate Technol., Shakopee, MN, USA
Abstract :
This work systematically explores the relationship between the resistive switching properties of Pr0.7Ca0.3MnO3 (PCMO) thin film element and its geometry dimensions in deep submicron (DSM) technologies. A series of PCMO-based resistive switch devices (RSDs) with different geometry sizes were fabricated. Our E-test results show that by reducing the PCMO layer thickness from the normal value of about 200 nm to 30 nm, a low switching voltage (within ±2.5 V) can be achieved. The reduction of PCMO layer thickness does not incur visible impact on device reliability: no significant degradation of two resistance states was observed after 1500 programming cycles. Based on the extrapolation from the measured electrical parameters of PCMO-based devices, we analyzed the design requirements of PCMO-based resistive memory with different cell structures in sub-100 nm technologies. Our simulations show that one-transistor-one-RSD (1T1R) cell structure can be successfully scaled down to 22 nm technology node. However, the scaling of one-non-ohmic-device-one-RSD (1N1R) cell structure is significantly limited by the low driving ability of current non-ohmic device technology.
Keywords :
calcium; electrical resistivity; manganese; praseodymium compounds; random-access storage; semiconductor thin films; semiconductor-metal boundaries; switching; DSM technology; PCMO layer thickness; PCMO thin film element; PCMO-based resistive memory; PCMO-based resistive switch device; PrCaMnO3; deep submicron; e-test; electrical parameter; extrapolation; geometry dimension; geometry size; one-nonohmic-device-one-RSD cell structure; one-transistor-one-RSD cell structure; resistive switching property; scalability; switching voltage; Degradation; Electric resistance; Electric variables measurement; Electrical resistance measurement; Extrapolation; Geometry; Low voltage; Scalability; Switches; Transistors;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450447