A novel probabilistic SET propagation method

In the current deep sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error result in an unacceptably large chip failure rate. We propose a method that considers gate delays to determine accurately the probability of SET propagation resulting into an error. Disjoint covers of appropriately formulated functions are used for the probability computations in order to consider reconvergent paths in the circuit. The probabilities are calculated at the output gate at all time instants that SET can propagate within a latching window. Bayes´ theorem is used to model the SET injection.