Title :
Advanced spice modeling for 65nm CMOS technology
Author :
Yang, Lianfeng ; Cui, Meng ; Ma, James ; He, Jia ; Wang, Wei ; Wong, Waisum
Author_Institution :
ProPlus Design Solutions, Inc., San Jose, CA, USA
Abstract :
The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65 nm CMOS process. STI-induced stress effect, well proximity effect, as well as HCI and NBTI reliability effects, which can not be neglected for technologies beyond 90 nm and must be properly modeled for accurate circuit simulations, are discussed in this study.
Keywords :
CMOS integrated circuits; SPICE; circuit reliability; circuit simulation; proximity effect (lithography); CMOS technology; HCI reliability effects; Hot Carrier Injection; NBTI reliability effects; SPICE modeling; STI-induced stress effect; circuit simulations; negative bias temperature instability; proximity effect; size 65 nm; CMOS process; CMOS technology; Capacitive sensors; Circuits; Degradation; Maintenance engineering; Proximity effect; Semiconductor device modeling; Stress; Threshold voltage;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-2185-5
Electronic_ISBN :
978-1-4244-2186-2
DOI :
10.1109/ICSICT.2008.4734568
