Super stretched solder interconnects for wafer level packaging

Author

Rajoo, R. ; Wong, E.H. ; Lim, S.S. ; Hnin, W.Y. ; Seah, S.K.W. ; Tay, A.A.O. ; Iyer, Mahadevan ; Tummala, Rao R.

Author_Institution

Inst. of Microelectron., Singapore

fYear

0

fDate

0-0 0

Abstract

A cost-effective wafer level packaging technique termed "stretch and break", based on stretching and detachment of solder interconnections, has been established. Excellent co-planarity, essential for wafer level test and burn-in, is inherent in the process. The technique allows the freedom to use solder materials of up to 400degC melting temperature for forming the interconnection. The shape of the interconnection can also be easily manipulated for optimum performance. The mechanical and thermal cycling reliabilities of the stretched solder interconnection have been found to be significantly better than those of conventional solder joints

Keywords

integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; solders; 400 C; mechanical reliability; melting temperature; solder interconnections; solder joints; solder materials; super stretched solder interconnects; thermal cycling reliability; wafer level packaging; wafer level test; Circuit testing; Copper; Costs; Flip chip; Integrated circuit interconnections; Packaging; Shape; Soldering; Thermal stresses; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2006. Proceedings. 56th

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

1-4244-0152-6

Type

conf

DOI

10.1109/ECTC.2006.1645809

Filename

1645809