Title :
Clock Gated Low Power Memory Implementation on Virtex-6 FPGA
Author :
Pandey, Bishwajeet ; Singh, D. ; Baghel, Deepak ; Yadav, J. ; Pattanaik, Manisha
Author_Institution :
Dept. of Inf. Technol., Indian Inst. of Inf. Technol., Gwalior, Gwalior, India
Abstract :
In this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in number of Signal and IO buffer due to Clock Gating, there is significant decrease in IO Power and Dynamic Power due to decrease in number of frequency of device operating. The increase in Logic Power and Signal Power is relatively small in magnitude than decrease in clock power that translates to decrease in overall dynamic power. The clock power consumption of Clock Gated 65536x16-bit dual-port RAM is 38.89%(on 1GHz) and 41.3%(on 10GHz) lesser than the clock power consumption of 65536x16-bit dual-port RAM without using clock gating Techniques.
Keywords :
clocks; field programmable gate arrays; logic design; random-access storage; randomised algorithms; FPGA device; IO buffer; IO power; ISE design tool; Virtex-6 FPGA; Xilinx ISE 14.1; clock gated 65536x16-bit dual-port RAM; clock gated low power memory implementation; clock gating techniques; clock power consumption; dynamic power; logic power; signal power; target design; Clocks; Field programmable gate arrays; Leakage currents; Logic gates; Memory management; Power demand; Random access memory; Clock Gating; Clock Power; Dual Port RAM; Dynamic Current; Dynamic Power; Logic Power; Signal Power;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2013 5th International Conference on
Conference_Location :
Mathura
DOI :
10.1109/CICN.2013.90
