Simulation of charge trapping memory with novel structures

The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al₂O₃ (15 nm)/Si₃Na (6.5 nm)/SiO₂ (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cell´s performance, the shape of gate stack is varied while keeping all other structural parameters fixed.