Author :
Pandey, Bishwajeet ; Yadav, J. ; Kumar, Jayant ; Kumar, Ravindra
Abstract :
In this paper, we apply clock gating technique in Global Reset ALU design on 28nm Artix7 FPGA to save dynamic and clock power both. This technique is simulated in Xilinx14.3 tool and implemented on 28nm Artix7 XC7A200T FFG1156-1 FPGA. When clock gating technique is not applied clock power contributes 32.25%, 4.24%, 3.06%, 3.09%, and 3.09% of overall dynamic power on 100 MHz, 1 GHz, 10 GHz, 100GHz and1 THz device frequency respectively. When clock gating technique is applied clock power contributes 0%, 1.02%, 1.06%, 1.06%, and 1.06% of overall dynamic power on 100 MHz, 1 GHz, 10 GHz, and 100GHz and1 THz device frequency respectively. With clock gating, there is 100%, 76.92%, 66.30%, 66.55% and 66.58% reduction in clock power in compare to clock power consumption without clock gate on 100 MHz, 1 GHz, 10 GHz, 100 GHz and 1 THz respectively operating frequency. Clock gating is more effective on 28nm in compare to 40nm and 90nm technology file.
Keywords :
UHF circuits; VHF circuits; clocks; field programmable gate arrays; low-power electronics; microwave circuits; millimetre wave circuits; submillimetre wave circuits; Artix7 XC7A200T FFG1156-1 FPGA; Xilinx14.3 simulated tool; clock gating aware low power global reset ALU design; frequency 1 GHz; frequency 1 THz; frequency 10 GHz; frequency 100 GHz; frequency 100 MHz; power consumption; size 28 nm; size 40 nm; size 90 nm; Clocks; Field programmable gate arrays; Latches; Logic gates; Power demand; Registers; Table lookup; Clock Gating; Device Operating Frequency; Dynamic Power Reduction; Global Reset ALU; Low Power; and FPGA;
