Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate

As semiconductor technology scales, manufacture process-related statistical variations and lifetime-dependent degradations contribute directly to the fluctuations of transistor parameters and circuit performances. Considering alone either the static process variation or the nominal lifetime degradation cannot ensure a robust design during the entire lifetime. It is thus highly necessary to obtain lifetime degradation information considering underlying process variation early at design phase. This paper establishes an innovative framework to predict the analog circuit behavior in its lifetime considering both process variations and degradation effects based on geometric lifetime yield analysis using worst-case distance degradation rate. Compared to Monte-Carlo-based methods and numerical optimization solutions, only performance and statistical parameter sensitivity analysis are required in the proposed framework.