A LVDS Transceiver Chip Design in 0.5 um CMOS Technology

The paper presents the design and implementation of input/output interface circuits, fully compatible with low-voltage differential signal (LVDS) standard. Due to the low voltage differential transmission technique, the low power consumption and high transmission speed are achieved at the same time. The transmitter is implemented by a closed-loop control circuit and an internal bandgap voltage reference, the receiver is implemented by means of a dual-gain stage folded cascode architecture. The transceiver is fabricated in 3.3 v and 5 v compatibly, 0.5 mum CMOS technology. The maximum transmission speed is up to 800 Mbps and quiescent current is only 5 mA.