Title :
An architecture with low memory-bandwidth and less hardware cost for 3SBM algorithm
Author :
Ming-Hwa Sheu ; Jau-Yien Lee ; Jhing-Fa Wang ; Liaug-Wei Lee ; Shyu-Ren Mau ; Liang-Ying Liu
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
The 3-step block matching (3SBM) algorithm has become one of the basic techniques in the area of motion estimation. The paper presents a pipeline architecture to perform this algorithm in real time. The major advantages of the architecture are (1) only two image memory modules are needed, (2) this architecture has less hardware cost and is suitable for VLSI implementation, (3) this architecture can be used in HDTV application.<>
Keywords :
VLSI; digital signal processing chips; high definition television; image sequences; motion estimation; parallel architectures; parameter estimation; real-time systems; search problems; 3-step block matching algorithm; 3SBM algorithm; HDTV application; VLSI implementation; hardware cost; image memory modules; memory-bandwidth; motion estimation; pipeline architecture; real time; Bandwidth; Computer architecture; Costs; Equations; HDTV; Hardware; Image coding; Memory architecture; Motion estimation; Pipelines;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.328048
