Title :
Scalable methods for the analysis and optimization of gate oxide breakdown
Author :
Fang, Jianxin ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of ECE, Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11× relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.
Keywords :
circuit optimisation; digital integrated circuits; electric breakdown; failure analysis; integrated circuit reliability; probability; analytic closed-form model; circuit failure; failure probability; gate oxide breakdown; gate sizing; large digital circuit; oxide reliability; posynomial-based optimization; ultra-pessimistic area-scaling method; Accuracy; Breakdown voltage; Calibration; Circuit testing; Digital circuits; Electric breakdown; MOSFETs; Optimization methods; Performance analysis; Stress;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450507
