• DocumentCode
    2145350
  • Title

    Analog placement and global routing considering wiring symmetry

  • Author

    Yang, Yu-Ming ; Jiang, Iris Hui-Ru

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    22-24 March 2010
  • Firstpage
    618
  • Lastpage
    623
  • Abstract
    Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer´s expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.
  • Keywords
    analogue integrated circuits; integrated circuit layout; analog design process; analog layout; analog placement; device symmetry constraint; digital layout generation; global routing algorithm; wiring symmetry; Breakdown voltage; Circuit testing; Digital circuits; Electric breakdown; MOSFETs; Optimization methods; Performance analysis; Routing; Stress; Wiring; Analog design automation; wiring symmetry;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2010 11th International Symposium on
  • Conference_Location
    San Jose, CA
  • ISSN
    1948-3287
  • Print_ISBN
    978-1-4244-6454-8
  • Type

    conf

  • DOI
    10.1109/ISQED.2010.5450510
  • Filename
    5450510