DocumentCode :
2145394
Title :
Fixed outline multi-bend bus driven floorplanning
Author :
Sheng, Wenxu ; Dong, Sheqin ; Wu, Yuliang ; Goto, Satoshi
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
2010
fDate :
22-24 March 2010
Firstpage :
632
Lastpage :
637
Abstract :
Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and bus-packing are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
Keywords :
circuit layout; integrated circuit design; system-on-chip; block-packing; bus routes; bus specification; bus-packing; deterministic algorithm; fixed outline multibend bus driven floorplanning; fixed-outline area; fixed-outline floorplanning; floorplan solution; hierarchical SOC design; interconnect constraint; less flexibility first algorithm; outline constraint; total bus area; total floorplan area; Algorithm design and analysis; Computational modeling; Computer science; Information science; Laboratories; Production systems; Routing; Shape; Space technology; Testing; Bus planning; Deterministic algorithm; Fixed outline; Floorplanning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
ISSN :
1948-3287
Print_ISBN :
978-1-4244-6454-8
Type :
conf
DOI :
10.1109/ISQED.2010.5450512
Filename :
5450512
Link To Document :
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