Title :
Multi-programming environment for structure under pads (SUP) and via arrays pattern recognition automated classification system
Author :
Yusof, Suraya Bt Mohd ; Lau Meng Tee
Author_Institution :
Batu Berendam Free Trade Zone, Nat. Semicond. Sdn.Bhd., Batu Berendam, Malaysia
Abstract :
In today\´s IC Design, EDA tools are not limited to IC designer\´s toys. The application of EDA has expanded into a larger scope including generation and extraction of critical information of a design for yield, quality and reliability analysis. Support for this expanded EDA role can necessitate the need for multi-platform programming as a single tool platform may not be capable. This paper illustrates an example of using multi-platform programming to classify vertically built structures under Bond pads and to categorize bond pad via array patterns both of which can be a DFM issue at assembly. The structure under the bond pad is analyzed using a layout verification tool which is proven for its capability and reliability. The tool generates a report classifying all bond pads in design layouts into one of six categories the "worst" case being PADs with active circuits under them. This information is critical for optimizing wafer sort and wire bond parameters to help ensure the reliability of the product. Via array pattern recognition is achieved using Object Oriented Programming Environment. Object Oriented Programming provides a fast proto-typing of ideas and provides ample flexibility for expansion and modularization. This tool digitizes the top via array into matrices of Os and Is and then generalizes into a description characterized as a "Bulls Eye", "Ring" or "Diamond" pattern.
Keywords :
electronic design automation; formal verification; integrated circuit design; object-oriented programming; pattern classification; automated classification system; bulls eye pattern; diamond pattern; electronic design automation; integrated circuit design; layout verification tool; multiprogramming environment; object oriented programming; ring pattern; structure under pads; via array pattern recognition; Active circuits; Assembly; Data mining; Design for manufacture; Electronic design automation and methodology; Information analysis; Object oriented programming; Pattern recognition; Wafer bonding; Wire; SUP; Via pattern recognition;
Conference_Titel :
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-6454-8
DOI :
10.1109/ISQED.2010.5450519