DocumentCode
2145777
Title
Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix
Author
Ezzat, Hicham ; Naviner, Lírida
Author_Institution
CNRS-LTCI, Inst. TELECOM - Telecom ParisTech, Paris, France
fYear
2010
fDate
22-24 March 2010
Firstpage
524
Lastpage
527
Abstract
As CMOS technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.
Keywords
CMOS logic circuits; fault simulation; integrated circuit design; integrated circuit reliability; nanoelectronics; probability; CMOS technology; circuit design; intermittent fault; level matrix propagation; logic circuit; nanometer scale; nanoscale circuit; probabilistic transfer matrix; reliability analysis; reliability degradation; reliability evaluation; transient fault; CMOS logic circuits; CMOS technology; Circuit analysis; Circuit faults; Integrated circuit reliability; Integrated circuit technology; Logic circuits; Logic gates; Scalability; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design (ISQED), 2010 11th International Symposium on
Conference_Location
San Jose, CA
ISSN
1948-3287
Print_ISBN
978-1-4244-6454-8
Type
conf
DOI
10.1109/ISQED.2010.5450527
Filename
5450527
Link To Document