Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits

Author

Hui-Wen Tsai ; Ming-Dou Ker

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

14

Issue

1

fYear

2014

fDate

Mar-14

Firstpage

493

Lastpage

498

Abstract

This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-μm 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.

Keywords

BiCMOS integrated circuits; failure analysis; integrated circuit layout; integrated circuit reliability; integrated circuit testing; power integrated circuits; BCD process; EOS failure prevention; IC manufacture production; bipolar CMOS DMOS process; circuit solution; electrical overstress failure; guard ring; high negative-current-latch-up immunity; high-voltage-applicable IC product; layout consideration; negative-current-triggered latchup test; power regulator IC; size 0.6 mum; voltage 40 V; Earth Observing System; Integrated circuits; Junctions; Layout; Logic gates; Materials reliability; Transistors; Electrical overstress (EOS); high-voltage CMOS; latchup; regulator;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2012.2206391

Filename

6226839