Multiple-input signature registers: an improved design

For testable design purposes, a multiple-output digital system needs a multiple-input signature register. This register accelerates the testing task by compressing multiple-input data streams into one signature. Existing designs depend on parallel feeding the input polynomials to the storage elements. These designs, give a good compression but, suffer from some drawbacks. The paper proposes a new design for the multiple-input signature register. This proposed design aggregates all inputs at a certain point and feeds them to the shift register. By adopting this concept, we are able to improve the operation of the multiple-input signature register in a number of ways. Complete VHDL modeling and simulation for the existing and the proposed designs verified the advantages of the new structure