Title :
A bit-serial systolic algorithm and VLSI implementation for RSA
Author :
Zhang, C.N. ; Xu, Y. ; Wu, C.C.
Author_Institution :
Dept. of Comput. Sci., Regina Univ., Sask., Canada
Abstract :
A new algorithm using delayed save adder representation and overflow determination technique for modular multiplication is presented. This algorithm can be implemented by a bit-serial systolic array for modular multiplications. A two level bit-serial systolic array for RSA is also designed and implemented. Our simulation and experimental chip design show that the proposed algorithm and its bit-serial implementation is suitable for VLSI, and a single RSA chip can be built to achieve much higher throughput
Keywords :
VLSI; adders; digital arithmetic; digital signal processing chips; parallel algorithms; public key cryptography; systolic arrays; 50 MHz; RSA; VLSI implementation; bit-serial systolic algorithm; bit-serial systolic array; clock rate; delayed save adder representation; experimental chip design; modular multiplication; overflow determination; public key cryptography; simulation; throughput; Added delay; Chip scale packaging; Clocks; Computer science; Hardware; Pipelines; Public key cryptography; Security; Systolic arrays; Very large scale integration;
Conference_Titel :
Communications, Computers and Signal Processing, 1997. 10 Years PACRIM 1987-1997 - Networking the Pacific Rim. 1997 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-3905-3
DOI :
10.1109/PACRIM.1997.620316
