DocumentCode
2146055
Title
A layout technique for millimeter-wave PA transistors
Author
Liang, ChuanKang ; Razavi, Behzad
Author_Institution
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
fYear
2011
fDate
5-7 June 2011
Firstpage
1
Lastpage
4
Abstract
The distributed interconnect parasitics within large transistors markedly degrade the output power and efficiency at millimeter-wave frequencies. This paper develops a model for such structures and proposes a layout technique to reduce the effect of source terminal parasitics. The technique is applied to a 60-GHz prototype in 65-nm CMOS technology, raising the output power from 5 to 10 dBm and the drain efficiency from 3.7% to 10.7%.
Keywords
CMOS analogue integrated circuits; circuit layout; millimetre wave power amplifiers; millimetre wave transistors; CMOS technology; distributed interconnect parasitics; frequency 60 GHz; layout technique; millimeter wave PA transistor; size 65 nm; source terminal parasitics; Inductance; Integrated circuit interconnections; Layout; Logic gates; Power generation; Resistance; Transistors; Millimeter-wave power amplifier; distributed parasitics; layout technique; power efficiency; source parasitics;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE
Conference_Location
Baltimore, MD
ISSN
1529-2517
Print_ISBN
978-1-4244-8293-1
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2011.5946225
Filename
5946225
Link To Document