Embedded erase failure in NOR flash EEPROM memory

Author

Lim, Bryan ; Wong, Vivien ; Gooi, L.C. ; Lee, Cecilia ; Francis, Caroline ; Lee, K.Y.

Author_Institution

Freescale Semicond., Petaling Jaya, Malaysia

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

843

Lastpage

845

Abstract

This paper presents the evaluation methods and findings of the hot temperature embedded erase failure on an embedded NOR flash EEPROM device. Automated Test Equipment (ATE) and bench evaluation revealed that the embedded erase failure was caused by compaction failure with high compaction pulse counts. Failure localization using memory bitmapping showed that the fail bitcells were populated at the edge of the flash array. Based on detailed electrical characterization and physical analysis, compaction failure was determined to be due to poor hot carrier injection (HCI) efficiency as a result of possible shallow trench isolation (STI) over-polish.

Keywords

automatic test equipment; flash memories; hot carriers; integrated circuit reliability; isolation technology; NOR flash EEPROM memory; automated test equipment; electrical characterization; embedded erase failure; failure localization; hot carrier injection; memory bitmapping; shallow trench isolation; Circuit testing; Compaction; EPROM; Failure analysis; Human computer interaction; Logic testing; Pulse amplifiers; Temperature; Test equipment; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734664

Filename

4734664