Improved high temperature retention and endurance in HfON trapping memory with double quantum barriers

Author

Chin, Albert ; Yang, H.J. ; Lin, S.H. ; Liao, C.C. ; Chen, W.J. ; Yeh, F.S.

Author_Institution

Electron. Eng. Dept., Nat´´l Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

811

Lastpage

814

Abstract

We have compared the device performance of double-quantum-barrier charge-trapping memory of a TaN/Ir₃Si-[HfAlO-LaAlO₃]-HfON_0.2-[HfAlO-SiO₂]-Si device with single barrier non-volatile memory MONOS devices at close EOT. At 150Â°C under fast 100 Â¿s and low Â±9 V P/E, the double-quantum-barrier charge-trapping device shows a 3.2 V initial Â¿V_th and 2.7 V 10-year extrapolated retention. This retention decay rate is much improved from single barrier device.

Keywords

digital storage; hafnium compounds; iridium compounds; lanthanum compounds; silicon compounds; tantalum compounds; temperature; TaN-Ir₃Si-(HfAlO-LaAlO₃)-HfON_0.2-(HfAlO-SiO₂)-Si; double quantum barrier; double-quantum-barrier charge-trapping memory; extrapolated retention; high temperature endurance; high temperature retention; single barrier nonvolatile memory MONOS device; temperature 150 C; Atherosclerosis; Circuits; Effective mass; Electron traps; High K dielectric materials; MONOS devices; Materials science and technology; Nonvolatile memory; SONOS devices; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734666

Filename

4734666