Simulation and measurement of high speed serial link performance in a dense, thin core flip chip package

The speed of differential digital signals, such as 12.5 Gb/s, have increased enough to be degraded by semiconductor packaging features which are ignored at lower frequencies. In addition, more and more signals need to communicate in and out of the die. Several multi-gigabit industry bus standards, like Hyper Transport, Infmiband, PCI Express, Rapid IO and SATA, are driving new speed and density specifications for differential signals. This paper will show how to meet these product requirements with a thin core, flip chip, organic package which uses a standard, reasonable-cost, reliable FR-4 type dielectric material