Analytical solutions for interconnect stress in board level drop impact

Author

Wong, E.H. ; Mai, Y.-W. ; Seah, S.K.W. ; Lim, K.M. ; Lim, T.B.

Author_Institution

Inst. of Microelectron., Singapore

fYear

0

fDate

0-0 0

Abstract

Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric design analysis; and (iii) establish an equivalent board for JEDEC drop test

Keywords

equivalent circuits; impact testing; integrated circuit interconnections; integrated circuit packaging; printed circuit testing; stress analysis; IC package; JEDEC drop test; PCB flexing; board level interconnection; closed form analytical solutions; degrees of symmetry; drop impact; equivalent board; interconnect stress; Boundary conditions; Differential equations; Electronics packaging; Integrated circuit modeling; Integrated circuit packaging; Integrated circuit testing; Materials science and technology; Microelectronics; Springs; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2006. Proceedings. 56th

Conference_Location

San Diego, CA

ISSN

0569-5503

Print_ISBN

1-4244-0152-6

Type

conf

DOI

10.1109/ECTC.2006.1645905

Filename

1645905