Title :
Multiprocessor revolution and cache management
Author :
Kapoor, Hemangee K.
Author_Institution :
Dept. of CSE, Indian Inst. of Technol., Guwahati, India
Abstract :
Advancement in semiconductor technology is allowing to pack more and more transistors on a single die, thus increasing the complexity of the systems. Chip density is continuing to increase approximately twice every two years. However, there is little instruction level parallelism left to improve the performance of a single processor. The clock speeds are also not increasing due to heat dissipation issues. The solution is to increase the number of cores on a chip instead of improving performance of single cores. More number of simple and small cores running at relatively slower clock rate can help to improve system performance by exploiting thread level parallelism. Threads of one or more applications can run on these multiple cores and communicate with each other to provide us with the end result. Communication among threads can be established using either message passing or shared memory.
Keywords :
cache storage; clocks; memory protocols; message passing; multi-threading; shared memory systems; cache coherence protocol; cache management; cache space utilization; chip density; chip multiprocessors; clock rate; clock speeds; heat dessipation; intruction level parallelism; logical cache clusters; logical core clusters; memory sharing; message passing; nonuniform access latencies; performance improvement; private caches; semiconductor technology; shared caches; shared data management; thread level parallelism; transistors;
Conference_Titel :
Emerging Trends and Applications in Computer Science (NCETACS), 2012 3rd National Conference on
Conference_Location :
Shillong
Print_ISBN :
978-1-4577-0749-0
DOI :
10.1109/NCETACS.2012.6203283