Analysis of contact resistance effect to SRAM performance in deep sub-micron technology

SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM¿s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis of SRAM Static Noise Margin (SNM) and its influence by contact resistance for a 6T SRAM bit cell. We also compare SNM for each generation of the process nodes from 0.25 um, 0.18 um, and 0.15 um, 0.13 um, to 0.09 um. We conclude that the contact resistance, alone with other process parameters, determines the SNM performance.