Title :
Design and performance of submicron MOSFETs on ultra-thin SOI for room temperature and cryogenic operation
Author :
Terrill, Kyle ; Woo, Jason ; Vasudev, P.K.
Author_Institution :
Hughes Res. Lab., Malibu, CA, USA
Abstract :
The performance of a mesa-isolated CMOS technology fabricated on ultrathin (nonepitaxial) SOI (silicon on insulator) with film thickness ranging from 850 to 1800 AA is presented. Overall the data show that there is no observable reduction in surface mobility as the silicon thickness is reduced to 850 AA, indicating that the scaling of devices into the deep-submicron regime is possible. The results of a two-dimensional analytical model which accounts for the effects of silicon film thickness, buried oxide thickness, gate oxide thickness, and back-gate bias on device performance are shown. The operation of a near-intrinsic MOSFET is studied at room temperature and cryogenic temperatures. Measurements show that with the application of back-gate bias this device is suitable for low-temperature operation.<>
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; semiconductor device models; semiconductor technology; 850 to 1800 A; SIMOX; Si thickness; Si-SiO/sub 2/; back-gate bias; buried oxide thickness; cryogenic operation; cryogenic temperatures; device design; device performance; film thickness; gate oxide thickness; low-temperature operation; mesa-isolated CMOS technology; near-intrinsic MOSFET; operation; room temperature operation; scaling of devices; submicron MOSFETs; surface mobility; two-dimensional analytical model; ultra-thin SOI; Annealing; Capacitance; Cryogenics; MOSFETs; Optical films; Semiconductor films; Silicon on insulator technology; Substrates; Temperature; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32815
