Optimization of Memory Allocation for H.264 Video Decoder on Digital Signal Processors

The computing power of microprocessors has exponentially increased in the past few decades, so the support to compute intensive multimedia applications has increased too. With such improved computing power, memory subsystem deficiency becomes the major barrier to support video decoder on the Digital Signal Processor (DSP). H.264/AVC becomes the next generation of video codec for embedded systems. In this paper, our focus is to enhance the decoding performance of H.264/AVC through memory optimization for DSP. The experimental results show that the proposed solutions can improve the H.264/AVC decoding speed by almost 37%. Also, the memory optimization method presented in this paper has been integrated into the developed embedded H.264/AVC video decoder. The decoder can perform real time decoding under eight channels of Common Intermediate Format (CIF) frame size, which is the typical requirement of networked video surveillance applications.