• DocumentCode
    2148054
  • Title

    Low error-floor majority-logic decoding based algorithm for non-binary LDPC codes

  • Author

    Song, Liyuan ; Zhang, Mu ; Huang, Qin ; Wang, Zulin

  • Author_Institution
    School of Electronic and Information Engineering, Beihang University, Beijing, China, 100191
  • fYear
    2015
  • fDate
    8-12 June 2015
  • Firstpage
    4072
  • Lastpage
    4076
  • Abstract
    The traditional majority-logic decoding (MLgD) based algorithms suffer error-floors for decoding non-binary LDPC codes with small column weights. This paper presents a bit-reliability based MLgD (BRB-MLgD) algorithm with low error-floors for non-binary LDPC codes. The proposed algorithm is carried out based on the binary representations of non-binary symbols. The reliability update along each edge of the Tanner graph of a non-binary LDPC code is in terms of bits rather than symbols. Thus, its computational complexity and memory consumption are less than those of the existing MLgD based algorithms. Simulation results indicate that the proposed algorithm can significantly reduce error-floors with small performance degradation in the waterfall region.
  • Keywords
    Computational complexity; Decoding; Iterative decoding; Memory management; Nickel; Reliability; Non-binary LDPC codes; bit-reliability; error-floor; majority-logic decoding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications (ICC), 2015 IEEE International Conference on
  • Conference_Location
    London, United Kingdom
  • Type

    conf

  • DOI
    10.1109/ICC.2015.7248961
  • Filename
    7248961