Author :
Yuan, J. ; Chan, V. ; Eller, M. ; Rovedo, N. ; Lee, H.K. ; Gao, Y. ; Sardesai, V. ; Kanike, N. ; Vidya, V. ; Kwon, O. ; Kwon, O.S. ; Yan, J. ; Fang, S. ; Wille, W. ; Wang, H. ; Chow, Y.T. ; Booth, R. ; Kebede, T. ; Clark, W. ; Mo, H. ; Ryou, C. ; Liang, J
Abstract :
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45°-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current as high as 650/320 uA/um at Ioff of 0.5 nA/um with Vdd=1.1V has been achieved for both NMOS and PMOS respectively. Ring oscillator speed (FO=1) has been boosted up by 30% with the device optimization. SRAM Vt mismatch is also improved by 10% with carbon co-IIP with good SRAM characteristics and low leakage current in 0.299 um2 cell.
Keywords :
MOS integrated circuits; SRAM chips; ion implantation; laser beam annealing; leakage currents; low-power electronics; optimisation; Jk:C; NMOS; PMOS; SRAM characteristics; carbon co-implantation; consumer electronics; device optimization; drive current; laser annealing; low leakage current; low power bulk technology; ring oscillator speed; rotated substrate; size 45 nm; wireless multimedia; Annealing; Costs; MOS devices; Power lasers; Random access memory; Research and development; Semiconductor device manufacture; Space technology; Substrates; Tensile stress;
