A study of 65nm BEOL trench etch issues

Author

Zhao, Lin-Lin ; Shen, Man-Hua ; Han, Qiu-Hua ; Zhang, Hai-Yang ; Chang, Shih-Mou

Author_Institution

Semicond. Manuf. Int. Corp., Shanghai, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1173

Lastpage

1176

Abstract

65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch process such as Rs, via resistance (Rc) and VBD. The feasible solutions and related etching mechanisms are also addressed for the above issues from the point view of the improvement of line-edge roughness (LER), within wafer AEI CDU (critical dimension uniformity) and interface conditions of via-bottom.

Keywords

copper; electrical resistivity; etching; integrated circuit interconnections; BEOL trench etch issues; Cu; breakdown voltage; copper surface; electrical parameter; etching mechanisms; line-edge roughness; metal resistance; size 65 nm; Chemicals; Copper; Dielectric materials; Electric resistance; Etching; Oxidation; Plasma applications; Plasma materials processing; Polymers; Strips;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734747

Filename

4734747