Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs

Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO₂/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 10¹³cm^-2, yielding values of 180 and 75 cm²/Vs at EOT = 0.65 and 0.8 nm respectively.