Programmable phase locked loops for digital signal processors

In systems of digital signal processors (array processors) the synchronization problems arise. In these systems the clock skew may be significant and may lead to the incorrect work of parallel algorithms. A clock skew can be eliminated by globally stable phase locked loops. Locally and globally stability of continuous and discrete phase locked loops for digital signal processors are considered. The parameters of period doubling bifurcations for discrete phase locked loop are obtained.