Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets

Assessment of global threshold voltage (V_th) variability in advanced silicon-on-insulator devices implies careful selection of a V_th extraction technique as different methods are sensitive to different parameters and effects. Our main focus is on experimental assessment of most widely used techniques, such as constant current, transconductance derivative and recently introduced g_m/I_d techniques. Some comparison with linear extrapolation methods is also provided. It is shown that g_m/I_d method, using data near threshold, is less sensitive to cross-impact of short channel effects (i.e. subthreshold slope and drain induced barrier lowering) variability. Therefore this method is preferred for extraction of intrinsic V_th variability without parasitic effects. Temperature evolution of global inter-die parameter variability is assessed for the first time. Possible reasons of slight variability temperature dependence are discussed.