Investigation and reduction of metal voids post-CMP in dual damascene process

Author

Nie, Jiaxiang ; Kang, Yun ; Yang, Ruipeng ; Su, Na ; He, Weiye ; Liu, Sheng ; Kong, Xiangtao

Author_Institution

Semicond. Manuf. Int. Corp., Shanghai, China

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

1223

Lastpage

1226

Abstract

Copper void density post copper CMP and defect reduction methods were investigated on 300 mm wafers of 65 nm node in this work. Effects of copper seed thickness, post-plating anneal temperature, FAB ambient and FOUP cleanliness on metal voids were examined. It was found that thinner seed thickness, lower anneal temperature with longer time post plating, high temperature de-gas or water rinse before copper plating, N₂ purge and special FOUP all resulted in reduced metal line void density.

Keywords

annealing; chemical mechanical polishing; metallisation; voids (solid); FAB ambient; FOUP cleanliness; copper seed thickness; dual damascene process; metal voids; post plating anneal temperature; size 300 mm; size 65 nm; Annealing; Chemical technology; Conductivity; Copper; Grain size; Helium; Manufacturing processes; Semiconductor device manufacture; Surface contamination; Temperature; Metal voids; VOC; anneal temperature; copper; dual damascene; seed thickness;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734768

Filename

4734768