A simple nano-scale patterning technology for FinFET fabrication

In this paper, a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally demonstrated. The technology is based on a micro-meter level lithography equipment, that is, it does not need any critical photolithographic step. The masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through a lateral etching in BOE. The etching rate is shown to slow down as the etching process goes on. A nano-scale oxide hard mask can be achieved after the nitride is removal. Both the cross-sectional view and top view of the etching process are shown by SEM photographs. Results indicate the simple patterning way is of low cost and under good control, and applicable to FinFET technology.