• DocumentCode
    2149540
  • Title

    Formal verification of analog circuit parameters across variation utilizing SAT

  • Author

    Miller, Merritt ; Brewer, Forrest

  • Author_Institution
    Department of Electrical and Computer Engineering, UCSB, USA
  • fYear
    2013
  • fDate
    18-22 March 2013
  • Firstpage
    1442
  • Lastpage
    1447
  • Abstract
    A fast technique for proving steady-state analog circuit operation constraints is described. Based on SAT, the technique is applicable to practical circuit design and modeling scenarios as it does not require algebraic device models. Despite the complexity of representing accurate transistor I/V characteristics, run-time and problem scaling behavior is excellent.
  • Keywords
    Analog circuits; Computational modeling; Data models; Integrated circuit modeling; Monte Carlo methods; Resistors; Transistors; Analog Verification; Circuit Modeling; Discrete Representation; SAT;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
  • Conference_Location
    Grenoble, France
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4673-5071-6
  • Type

    conf

  • DOI
    10.7873/DATE.2013.294
  • Filename
    6513740
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2149540