Design of low power differential logic using adiabatic switching technique

Author

Lo, Chun-Keung ; Chan, Philip C.H.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

33

Abstract

This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range

Keywords

adders; logic design; adiabatic differential cascode voltage switch; adiabatic logic circuit; adiabatic switching; complementary pass-transistor logic tree; design; energy dissipation; energy recovery; low power differential logic; pipelined ADCPL carry lookahead adder; simulation; supply clock; Adders; CMOS logic circuits; Circuit simulation; Clocks; Energy dissipation; Logic circuits; Logic design; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706807

Filename

706807