A submicron InAlAs/n+-InP HFET with reduced impact ionization

We have fabricated submicron InAlAs/n⁺-InP HFETs that employ an InP channel layer to eliminate impact ionization and thus reduce gate leakage, decrease drain conductance, and improve breakdown voltage. Under typical bias conditions, our L_g=0.8 μm devices achieve a low g_d of 5.1 mS/mm, leading to a voltage gain of 25, while the gate current never exceeds 17 μA/mm. This is approximately a 60 times lower gate current than for typical InAlAs/InGaAs HEMTs, including edge isolated devices. Off-state drain source breakdown voltage is about 10 V at 1 mA/mm and increases as the device is turned on, confirming that impact ionization is negligible. Our results on a lattice-matched structure suggest considerable potential for optimization by using a strained insulator layer to reduce gate leakage and to improve breakdown still further